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25A512
2.8
PAGE ERASE
The PAGE ERASE instruction will erase all bits (FFh)
inside the given page. A Write Enable ( WREN ) instruc-
tion must be given prior to attempting a PAGE ERASE .
This is done by setting CS low and then clocking out
the proper instruction into the 25A512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The PAGE ERASE instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
CS must then be driven high after the last bit of the
address or the PAGE ERASE will not execute. Once
the CS is driven high the self-timed PAGE ERASE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the PAGE ERASE cycle
is complete.
If a PAGE ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
FIGURE 2-8:
CS
PAGE ERASE SEQUENCE
0
1
2
3
4
5
6
7
8
9 1 0 11
2 1 2 2 2 3
SCK
Instruction
16-bit Address
SI
1
1
0
1
1
0
0
0 15 14 13 12
2
1
0
High-Impedance
SO
? 2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 15
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